Multi-layered structures comprising a device layer with a device quality surface, such as a silicon-geranium or sapphire layer, and a silicon substrate that has a different crystal lattice structure than the material of the device layer are useful for a number of different purposes. These multi-layered structures typically comprise multiple layers of material having differing coefficients of thermal expansion. During manufacture of such structures, however, the different rates of thermal expansion can create very large stresses in the multilayered structures when they are heated, which can fracture the device layer or substrate. This places severe constraints on the maximum temperature that these dissimilar pairs can be exposed to during manufacture.
Multi-layered structures comprising a device quality layer bonded to a substrate may be fabricated or manufactured in a number of ways. For example, in one approach, the multi-layered structure may be formed by direct layer transfer. In this process, an implanted wafer is bonded directly to the substrate, subjected to a low temperature anneal, and cleaved thermally and/or mechanically to result in a thin, but rough, layer on the surface of the substrate. The rough layer must then be smoothed. Some degree of smoothing may be done using a chemo-mechanical polishing step at relatively low temperatures. However, chemo-mechanical polishing is generally not suitable to achieve the uniformity required for state of the art multilayered structures and is therefore not desirable. Thermal methods may also be used to thin and smooth a wafer surface; however, while thermal methods easily achieve film target thicknesses, uniformity, and smoothness, they require that the wafer be heated to high temperatures, which damage the crystallinity of the film due to the aforementioned stresses.
Another method by which such multi-layered structures may be fabricated or manufactured while solving the smoothing problem includes bonding a silicon on insulator wafer to the dissimilar substrate and subjecting both to a low temperature bond strengthening anneal. (See, e.g., D. V. Singh, L. Shi, K. W. Guarni, P. M. Mooney, S. J. Koester, and A. Grill, “Electronic Materials” Vol. 32, no. 11, pg. 1339, 2003). The handle wafer may then be ground or etched down to the BOX layer and the BOX layer is removed by a hydrofluoric etch. The exposed silicon layer surface then has the same thickness as the starting silicon-on-insulator wafer and the finally exposed surface has roughness similar to a polished surface with no chemo-mechanical polishing or thermal step needed. Preparing a multi-layer structure in this way, however, is not without problems. For example, as the entire handle wafer must be ground or etched away, the process can become both time consuming and costly.